Company Description:
Trusted Semiconductor Solutions provides integrated circuit development services from concept to qualified part delivery leveraging the best-in-class on-shore manufacturing capabilities. Trusted Semiconductor Solutions specializes in IC design and high-density package solutions with expertise in radiation hardening for space and strategic applications. Trusted Semiconductor Solutions is a Trusted accredited supplier and a non-traditional defense contractor. For more information, please visit: www.trustedsemi.com.
Trusted Semiconductor Solutions has an immediate opening for an experienced Physical Layout Engineer.
Please Note: Only applicants with a current status of U.S. Citizen, U.S. Permanent Resident, Political Asylee, or Refugee will be considered for this position.
Job Description:
As a FinFET Physical Layout Engineer, you’ll play a crucial role in translating circuit designs into physical layouts. You’ll work closely with analog and mixed-signal design teams, ensuring that our custom-designed chips meet performance, power, and area targets. Additional duties include the evaluation of customer requirements, estimating effort/expenses for projects, development of test/characterization plans and datasheets, participation in debug and root cause analysis efforts, and engaging with the quality team to improve design processes/methodologies.
Essential Duties and Qualifications:
Layout Development:
- Create and optimize physical layouts for analog and mixed-signal blocks using FinFET technology.
- Collaborate with circuit designers to understand design requirements and constraints.
- Implement layout floorplans, place, and route components, and perform layout verification.
Analog and Mixed-Signal Expertise:
- Design custom layouts for analog building blocks such as LNAs, mixers, amplifiers, VCOs, and PLLs.
- Optimize layouts for performance, noise, and parasitics.
- Ensure compliance with design rules and DRC/LVS checks.
FinFET Technology:
- Work with advanced process nodes (e.g., 16nm, 7nm, or below) using FinFET transistors.
- Understand FinFET-specific layout considerations (e.g., fin pitch, gate pitch, and contact/via rules).
Layout Verification:
- Perform layout extraction, parasitic extraction, and post-layout simulations.
- Collaborate with verification engineers to ensure layout correctness and functionality.
Physical Verification and Closure:
- Run DRC (Design Rule Check) and LVS (Layout vs. Schematic) checks.
- Address any violations and achieve layout closure.
Qualifications:
- Bachelors/master’s in electrical engineering/computer science or equivalent.
- 5+ years of direct industry experience with analog and mixed signal layout.
- Preferred work on-site at our Minnesota offices.
- Strong design experience using Cadence PDKs.
- Proficiency in layout tools (e.g. Cadence Virtuoso, Synopsys IC Compiler).
- Knowledge of OS Linux, scripting languages – e.g., Python, Shell, TCL.
- A self-starter with the ability to assume leadership roles.
- Ability to work well in a diverse team environment.
- Experience with industry standard development tools and methodologies.
Target Annual Salary:
- The US base salary range for this full-time position is $80,000-$150,000.
Location:
- Work at the TSS office in Brooklyn Park, MN is strongly preferred. Willing to consider remote work.
Benefits:
- Health insurance
- Dental insurance
- 401K Plan with profit sharing
- Paid Time Off (PTO)
- Stock option plan