ASIC Design, Front-End
HDL through Synthesis
- RTL coding (VHDL and Verilog)
- Simulation
- Logic synthesis and STA
- Test bench development
- Test insertion and test vector generation
- Strong written and oral communication skills
- Synopsys and Cadence EDA tools experience
- 10+ years of experience preferred
- U.S. citizenship required
ASIC Design, Back-End
Physical design and verification
- Floorplanning
- Cell placement
- Clock and signal routing
- Physical verification (LVS/DRC)
- Experience with <45nm technology
- Strong written and oral communication skills
- Synopsys, Cadence, and Mentor EDA tools experience
- 10+ years of experience preferred
- U.S. citizenship required
Layout Engineer
Custom IC layout
- Floorplanning
- Custom physical design and routing
- Extraction and physical verification
- Experience with analog, mixed-signal, and RF layouts
- Strong written and oral communication skills
- Experience with Cadence EDA tools
- 10+ years of experience preferred
- U.S. citizenship required
Circuit Designer
Analog/mixed-signal ASIC design
- Design of amplifiers, data converters, SerDes, PLLs, memories, or high-frequency circuits
- SPICE modeling and simulation
- Testbench development
- Strong written and oral communication skills
- Experience with Cadence EDA tools
- 10+ years of experience preferred
- U.S. citizenship required